On Wed, Jun 27, 2018 at 07:27:21PM +0800, Robert Hoo wrote: > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as > SPEC_CTRL. > > Signed-off-by: Robert Hoo <robert...@linux.intel.com>
Based on kernel commit 1eaafe91, it looks like we must always set IA32_ARCH_CAPABILITIES.RSBA[bit 2] unless we're really sure the VM will not be migrated to a vulnerable processor. Considering this, I'd like to make "+arch-capabilities" set IA32_ARCH_CAPABILITIES.RSBA by default, unless RSBA is explicitly disabled by management software. > --- > target/i386/cpu.c | 2 +- > target/i386/cpu.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index e6c2f8a..953098c 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -1002,7 +1002,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] > = { > NULL, NULL, NULL, NULL, > NULL, NULL, NULL, NULL, > NULL, NULL, "spec-ctrl", NULL, > - NULL, NULL, NULL, "ssbd", > + NULL, "arch-capabilities", NULL, "ssbd", > }, > .cpuid_eax = 7, > .cpuid_needs_ecx = true, .cpuid_ecx = 0, > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 734a73e..1ef2040 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -688,6 +688,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network > Instructions */ > #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply > Accumulation Single Precision */ > #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ > +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities of > RDCL_NO and IBRS_ALL*/ > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass > Disable */ > > #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction > Barrier */ > -- > 1.8.3.1 > > -- Eduardo