From: Yongbok Kim <yongbok....@mips.com> MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only, and placing ELPA flag checks befor switch statement were technically correct. However, after adding handling more registers, these checks should be moved to act only in cases of handling EntryLo0 and EntryLo1.
Signed-off-by: Yongbok Kim <yongbok....@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.marko...@wavecomp.com> --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index aee39d0..57e24f3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4884,12 +4884,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *rn = "invalid"; - CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); - switch (reg) { case 2: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); rn = "EntryLo0"; break; @@ -4900,6 +4899,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 3: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); rn = "EntryLo1"; break; @@ -4964,12 +4964,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *rn = "invalid"; uint64_t mask = ctx->PAMask >> 36; - CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); - switch (reg) { case 2: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); tcg_gen_andi_tl(arg, arg, mask); gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); rn = "EntryLo0"; @@ -4981,6 +4980,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 3: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); tcg_gen_andi_tl(arg, arg, mask); gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); rn = "EntryLo1"; -- 2.7.4