Subject: [PATCH v2 06/33] target/mips: Add emulation of some common nanoMIPS
32-bit instructions
From: Yongbok Kim <yongbok....@mips.com>
Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC,
ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions.
Signed-off-by: Yongbok Kim <yongbok....@mips.com>
Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com>
Signed-off-by: Stefan Markovic <smarko...@wavecomp.com>
---
target/mips/translate.c | 285 +++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 284 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 379b6ba..09bb9b2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
+ case NM_SEQI:
+ {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_local_new();
+ TCGLabel *l1 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ tcg_gen_movi_tl(t1, extract32(ctx->opcode, 0, 12));
+ tcg_gen_movi_tl(t2, 0);
+ tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
+ tcg_gen_movi_tl(t2, 1);
+ gen_set_label(l1);
+ gen_store_gpr(t2, rt);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ }
+ break;
+ case NM_ADDIUNEG:
+ {
+ int16_t imm;
+ imm = (int16_t) extract32(ctx->opcode, 0, 12);
+ gen_arith_imm(ctx, OPC_ADDIU, rt, rs, -imm);
+ }
+ break;
+ case NM_P_SHIFT:
+ {
+ int shift = extract32(ctx->opcode, 0, 5);
+ switch ((ctx->opcode >> 5) & 0x0f) {
+ case NM_P_SLL:
+ if (rt == 0 && shift == 0) {
+ /* NOP */
+ } else if (rt == 0 && shift == 3) {
+ /* EHB treat as NOP */
+ } else if (rt == 0 && shift == 5) {
+ /* PAUSE */
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ } else if (rt == 0 && shift == 6) {
+ /* SYNC */
+ check_insn(ctx, ISA_MIPS2);
+ /* Treat as NOP. */
+ } else {
+ /* SLL */
+ gen_shift_imm(ctx, OPC_SLL, rt, rs,
+ extract32(ctx->opcode, 0, 5));
+ }
+ break;
+ case NM_SRL:
+ gen_shift_imm(ctx, OPC_SRL, rt, rs,
+ extract32(ctx->opcode, 0, 5));
+ break;
+ case NM_SRA:
+ gen_shift_imm(ctx, OPC_SRA, rt, rs,
+ extract32(ctx->opcode, 0, 5));
+ break;
+ case NM_ROTR:
+ gen_shift_imm(ctx, OPC_ROTR, rt, rs,
+ extract32(ctx->opcode, 0, 5));
+ break;
+ }
+ }
+ break;
Indentation is wrong for these "cases".
Otherwise:
Reviewed-by: Aleksandar Markovic <amarko...@wavecomp.com>
