On Sat, Jul 28, 2018 at 11:49 AM, Alistair Francis <alistair.fran...@wdc.com > wrote:
> Allow QEMU to be built to run on a RISC-V host. > > QEMU does not yet have a RISC-V TCG or user mode target port, but > running other architectures on RISC-V using TCI does work. > There is this RISC-V TCG backend here: https://github.com/riscv/riscv-qemu/tree/wip-riscv-tcg-backend I realized I had not sent an update to the list. There is a working TCG backend for RISC-V: - I've so far tested it with user-mode translation only. - It does not support large guests e.g. 64-bit hosts on riscv32. - The softmmu implementation is there but needs testing. - Some things are missing, e.g. memory fences. big-endian support You might find some other relevant changes in the configure hunks in the patch. IIRC there were a few changes to configure, one of them was to get the riscv disassembler working. Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > --- > configure | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/configure b/configure > index 2a7796ea80..c3ff3ae146 100755 > --- a/configure > +++ b/configure > @@ -606,6 +606,16 @@ EOF > compile_object > } > > +check_define_value() { > +cat > $TMPC <<EOF > +#if (($1) != ($2)) > +#error $1 != ($2) > +#endif > +int main(void) { return 0; } > +EOF > + compile_object > +} > + > check_include() { > cat > $TMPC <<EOF > #include <$1> > @@ -704,6 +714,12 @@ elif check_define __arm__ ; then > cpu="arm" > elif check_define __aarch64__ ; then > cpu="aarch64" > +elif check_define __riscv ; then > + if check_define_value __riscv_xlen 64 ; then > + cpu="riscv64" > + else > + cpu="riscv32" > + fi > else > cpu=$(uname -m) > fi > @@ -712,7 +728,7 @@ ARCH= > # Normalise host CPU name and set ARCH. > # Note that this case should only have supported host CPUs, not guests. > case "$cpu" in > - ppc|ppc64|s390|s390x|sparc64|x32) > + ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64) > cpu="$cpu" > supported_cpu="yes" > eval "cross_cc_${cpu}=\$host_cc" > -- > 2.17.1 > >