On 26 July 2018 at 20:31, Julia Suvorova <jus...@mail.ru> wrote: >> +++ b/hw/arm/nrf51_soc.c
>> +static void nrf51_soc_init(Object *obj) >> +{ >> + NRF51State *s = NRF51_SOC(obj); >> + >> + memory_region_init(&s->container, obj, "nrf51-container", >> UINT64_MAX); >> + >> + object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARM_M_PROFILE); >> + object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), >> &error_abort); >> + qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default()); >> + qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", >> ARM_CPU_TYPE_NAME("cortex-m0")); >> + qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 96); > > > Where did this number come from? ARMv6-M NVIC supports only 32 interrupts. I think this was left over from when I was first creating a m0 based system (efm32hg) over a year ago. Good catch. I couldn't see a table of valid interrupts in the nrf51 datasheet. Are you able to find this information? If not, I will re-spin with the number of irqs set to 32. Cheers, Joel