On 25 July 2018 at 09:59, Stefan Hajnoczi <stefa...@redhat.com> wrote:
> Define a "cortex-m0" ARMv6-M CPU model.
>
> Most of the register reset values set by other CPU models are not
> relevant for the cut-down ARMv6-M architecture.
>
> Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
> ---
> target/arm/cpu.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 3848ef46aa..7e477c0d23 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1255,6 +1255,15 @@ static void arm11mpcore_initfn(Object *obj)
> cpu->reset_auxcr = 1;
> }
>
> +static void cortex_m0_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> + set_feature(&cpu->env, ARM_FEATURE_V6);
> + set_feature(&cpu->env, ARM_FEATURE_M);
> +
> + cpu->midr = 0x410cc200;
> +}
We have all the patches for turning off not-v6M bits of
behaviour either in master or in target-arm.for-3.1 already,
right?
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
