On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> +static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
> + int ret, int v1, int v2)
> +{
> + TCGv t0;
> + TCGv v0_t;
> + TCGv v1_t;
> +
> + t0 = tcg_temp_new();
> +
> + v0_t = tcg_temp_new();
> + v1_t = tcg_temp_new();
> +
> + gen_load_gpr(v0_t, ret);
Again with loading a result,
> + gen_load_gpr(v1_t, v1);
> +
> + switch (opc) {
> + case NM_ABSQ_S_QB:
> + check_dspr2(ctx);
> + gen_helper_absq_s_qb(cpu_gpr[ret], v0_t, cpu_env);
> + break;
and unprotected use of cpu_gpr[0].
r~
