> From: Aleksandar Markovic <aleksandar.marko...@rt-rk.com> > Sent: Monday, August 13, 2018 7:52 PM > To: qemu-devel@nongnu.org > > Subject: [PATCH v8 10/87] target/mips: Fix MT ASE instructions' availability > control > > From: Aleksandar Rikalo <arik...@wavecomp.com> > > Use bits from configuration registers for availability control > of MT ASE instructions, rather than only ISA_MT bit in insn_flags. > > Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com> > Signed-off-by: Stefan Markovic <smarko...@wavecomp.com> > --- > target/mips/translate.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/mips/translate.c b/target/mips/translate.c > index b73f434..af9714b 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -8393,7 +8393,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext > *ctx, uint32_t opc, int rt, > opn = "mthc0"; > break; > case OPC_MFTR: > - check_insn(ctx, ASE_MT); > + check_cp0_enabled(ctx); > if (rd == 0) { > /* Treat as NOP. */ > return; > @@ -8403,7 +8403,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext > *ctx, uint32_t opc, int rt, > opn = "mftr"; > break; > case OPC_MTTR: > - check_insn(ctx, ASE_MT); > + check_cp0_enabled(ctx); > gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, > ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); > opn = "mttr"; > @@ -18619,7 +18619,7 @@ static void decode_opc_special3(CPUMIPSState *env, > DisasContext *ctx) > gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); > break; > case OPC_FORK: > - check_insn(ctx, ASE_MT); > + check_mt(ctx); > { > TCGv t0 = tcg_temp_new(); > TCGv t1 = tcg_temp_new(); > @@ -18632,7 +18632,7 @@ static void decode_opc_special3(CPUMIPSState *env, > DisasContext *ctx) > } > break; > case OPC_YIELD: > - check_insn(ctx, ASE_MT); > + check_mt(ctx); > { > TCGv t0 = tcg_temp_new(); > > @@ -19929,22 +19929,22 @@ static void decode_opc(CPUMIPSState *env, > DisasContext *ctx) > op2 = MASK_MFMC0(ctx->opcode); > switch (op2) { > case OPC_DMT: > - check_insn(ctx, ASE_MT); > + check_cp0_mt(ctx); > gen_helper_dmt(t0); > gen_store_gpr(t0, rt); > break; > case OPC_EMT: > - check_insn(ctx, ASE_MT); > + check_cp0_mt(ctx); > gen_helper_emt(t0); > gen_store_gpr(t0, rt); > break; > case OPC_DVPE: > - check_insn(ctx, ASE_MT); > + check_cp0_mt(ctx); > gen_helper_dvpe(t0, cpu_env); > gen_store_gpr(t0, rt); > break; > case OPC_EVPE: > - check_insn(ctx, ASE_MT); > + check_cp0_mt(ctx); > gen_helper_evpe(t0, cpu_env); > gen_store_gpr(t0, rt); > break;
Reviewed-by: Aleksandar Markovic <amarko...@wavecomp.com>