On 22 August 2018 at 09:15, Luc Michel <luc.mic...@greensocs.com> wrote: > > > On 8/21/18 3:28 PM, Peter Maydell wrote: >> The GICv2's QEMU interface (sysbus MMIO regions, IRQs, >> etc) is now quite complicated with the addition of the >> virtualization extensions. Add a comment in the header >> file which documents it. >> >> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> >> --- >> I needed to write this out to figure out what I was >> connecting to what in the a15mpcore object :-) >> --- >> include/hw/intc/arm_gic.h | 35 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 35 insertions(+) >> >> diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h >> index 42bb535fd45..989bc837606 100644 >> --- a/include/hw/intc/arm_gic.h >> +++ b/include/hw/intc/arm_gic.h >> @@ -18,6 +18,41 @@ >> * with this program; if not, see <http://www.gnu.org/licenses/>. >> */ >> >> +/* >> + * QEMU interface: >> + * + QOM property "num-cpu": number of CPUs to support >> + * + QOM property "num-irq": number of IRQs (including both SPIs and PPIs) >> + * + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore >> GIC >> + * + QOM property "has-security-extensions": set true if the GIC should >> + * implement the security extensions >> + * + QOM property "has-virtualization-extensions": set true if the GIC >> should >> + * implement the virtualization extensions >> + * + unnamed GPIO inputs: (where P is number of PPIs, i.e. num-irq - 32) > "where P is the number of SPIs" >> + * [0..P-1] SPIs >> + * [P..P+31] PPIs for CPU 0 >> + * [P+32..P+63] PPIs for CPU 1 >> + * ... >> + * + sysbus IRQ 0 : IRQ >> + * + sysbus IRQ 1 : FIQ >> + * + sysbus IRQ 2 : VIRQ (exists even if virt extensions not present) >> + * + sysbus IRQ 3 : VFIQ (exists even if virt extensions not present) >> + * + sysbus IRQ 4 : maintenance IRQ for CPU i/f 0 (only if virt extns >> present) >> + * + sysbus IRQ 5 : maintenance IRQ for CPU i/f 1 (only if virt extns >> present) > I think it's more like > > For a GIC supporting N CPUs: > + sysbus IRQ 0: IRQ for CPU 0 > + ... > + sysbus IRQ N-1: IRQ for CPU N-1 > > + sysbus IRQ N: FIQ for CPU 0 > + ... > + sysbus IRQ 2*N-1: FIQ for CPU N-1 > > + sysbus IRQ 2*N: VIRQ for CPU 0 > + ... > + sysbus IRQ 3*N-1: VIRQ for CPU N-1 > > + sysbus IRQ 3*N: VFIQ for CPU 0 > + ... > + sysbus IRQ 4*N-1: VFIQ for CPU N-1 > > + sysbus IRQ 4*N: maintenance IRQ for CPU i/f 0 (only if virt extns > present) > + ... > + sysbus IRQ 5*N-1: maintenance IRQ for CPU i/f N-1 (only if virt > extns present)
Yes, indeed. Since this is just a comment patch, I'll apply 2-9 from this series to target-arm.next and respin this patch. Thanks for the review. -- PMM