On Thu., Aug. 23, 2018, 2:20 p.m. Peter Maydell, <peter.mayd...@linaro.org> wrote:
> On 23 August 2018 at 17:36, Christopher Friedt <chrisfri...@gmail.com> > wrote: > > Hi; thanks for your patch, but I don't think it is correct. > What it does is to make QEMU ignore the T bit in the xPSR. > The architecture says that what should happen is that attempts > to execute with the T bit clear should cause an INVSTATE > UsageFault, which is exactly what we do. The reason we end up > aborting is because the CPU should really be going into > Lockup mode (where it basically hangs indefinitely), > and QEMU doesn't implement that. > > Your guest code almost certainly has a bug where it is > not setting the low bit in the words in its exception > vector table. See the v7M ARM ARM section B1.5.3 if you > happen to have a copy on your lake, but the short answer > is that bit 1 must be set, exactly because this is what > defines whether EPSR.T is set on exception entry. If > you tried this on real hardware it would fail in the > same way (except that the hardware would lock up and sit > there like a lemon rather than calling abort()). > Doh! You're right, although I checked for that in my rom vector table. As it turns out, I relocated my vtable to ram and *then* zeroed bss, which would obviously clear the T bit. Cheers ;-) >
