>On Mon, Aug 27, 2018 at 04:25:00PM +0800, peng.h...@zte.com.cn wrote: >> >> On 25 Aug 2018, at 15:19, Peng Hao <peng.h...@zte.com.cn> wrote: >> >> >> >> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c >> >> index 0e60834..da73743 100644 >> >> --- a/hw/pci-host/piix.c >> >> +++ b/hw/pci-host/piix.c >> >> @@ -327,6 +327,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, >> >> Error **errp) >> >> >> >> sysbus_add_io(sbd, 0xcfc, &s->data_mem); >> >> sysbus_init_ioports(sbd, 0xcfc, 4); >> >> + >> >> + /* register i440fx 0xcf8 port as coalesced pio */ >> >> + memory_region_set_flush_coalesced(&s->data_mem); >> >> + memory_region_add_coalescing(&s->conf_mem, 0, 4); >> >> } >> >> >> >Is there a reason to not register this port as coalesced PIO also for Q35? >> >In q35_host_realize()? >> >If not, I would do that as an extra patch as part of this series. >> Just as I mentioned in patch [0/4] , you can add pci->>host config port as >> coalesecd pio. I think it works for q35 port 0xcf8. >> >-Liran > >What's the performance improvement for q35? q35 also has the same pci-host config port 0xcf8 as piix. I test the coalesced pio for q35 pci-host config port 0xcf8. It spent less VM-exit avg time from 3us to 0.6us.
>-- >MST
