On 07/09/2018 08:32, Li Qiang wrote: > Hello all, > > I want to know why the i440FX in the following 'info qtree' information is > laid under the pci.0 bus. In the chip spec here: > -->https://wiki.qemu.org/images/b/bb/29054901.pdf > I don't see this device. > > Can anyone give me some hints?
Hi, the device implements what is in "3.2. PCI Configuration Space Mapped Registers" in the i440FX spec. Paolo
