On Tue, Oct 09, 2018 at 03:40:13PM +0200, Laurent Desnogues wrote: > Hello, > > On Tue, Oct 9, 2018 at 3:19 PM Edgar E. Iglesias > <edgar.igles...@xilinx.com> wrote: > > > > Another A72 related thing I wanted to check with you. A month or two ago I > > was > > looking at an issue with Linux running very slowly on our models. > > Something that popped up was that Linux was running a couple of spectre > > related > > "workarounds" and "hardening" sequences on the QEMU A72s. > > > > There are a couple of bits in the ID_AARCH64_PFR0 register that > > Linux checks before enabling the sequences but I never found any > > documentation of them in the specs. Bits 56 and 60. > > > > In Linux these are refered to as: > > ID_AA64PFR0_CSV2_SHIFT > > ID_AA64PFR0_CSV3_SHIFT > > > > This is what we have in our tree: > > > > cpu->gic_vprebits = 5; > > define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); > > > > /* Xilinx FIXUPs. */ > > /* These indicate the BP hardening and KPTI aren't needed. */ > > cpu->id_aa64pfr0 |= (uint64_t)1 << 56; /* BP. */ > > cpu->id_aa64pfr0 |= (uint64_t)1 << 60; /* KPTI. */ > > } > > > > Do you know what these are? > > Should we be setting these in QEMU? > > These fields are publicly documented in the system register specification: > > https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools > > These are ARMv8.5 fields, I don't think these should be set by default > for Cortex-A72. Of course nothing prevents you from defining a > specific CPU with these fields set to boot faster :-) Or perhaps add > a property to override the default value of these registers?
Thanks, I had no idea these documents existed! Cheers, Edgar
