On 8 November 2018 at 18:52, Palmer Dabbelt <pal...@sifive.com> wrote: > On Thu, 08 Nov 2018 10:38:51 PST (-0800), alistai...@gmail.com wrote: >> >> On Thu, Nov 8, 2018 at 10:35 AM Palmer Dabbelt <pal...@sifive.com> wrote: >>> >>> >>> The following changes since commit >>> a7ce790a029bd94eb320d8c69f38900f5233997e: >>> >>> tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +0000) >>> >>> are available in the Git repository at: >>> >>> git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-rc1 >>> >>> for you to fetch changes up to 00a014ac01feac875468d38c376f7e06f050f992: >>> >>> riscv: spike: Fix memory leak in the board init (2018-11-08 08:41:06 >>> -0800) >>> >>> ---------------------------------------------------------------- >>> A Single RISC-V Patch for 3.1-rc1 >>> >>> This tag contains a single patch that I'd like to target for rc1: a fix >>> for a memory leak that was detected by static code analysis. >>> >>> There are still three patch sets that I'd like to try to get up for 3.1: >>> >>> * The patch set Basian just published that contains fixes for a pair of >>> issues he found when converting our port to decodetree. >>> * An as-of-yet-unwritten fix to the third issue that Basian pointed out. >>> * A fix to our fflags bug, which is currently coupled to some CSR >>> refactoring that I don't think is OK for 3.1. >> >> >> There is one more patch fixing a memory leak in the virt board as well. > > > Oh, sorry about that -- I thought they were the same patch! > > Peter: let me know if you want me to submit a new copy of this PR with both > patches or a follow-on PR. Sorry for the noise!
As it happens, I'd just run this pullreq through testing overnight, so I've pushed it to master; you can send another one with the other patch. thanks -- PMM
