On 8 November 2018 at 17:52, Richard Henderson
<richard.hender...@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
> * we know these will only support creating one kind of guest CPU,
> * which is its preferred CPU type. Fortunately these old kernels
> @@ -474,8 +497,71 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
> *ahcf)
> ahcf->target = init.target;
> ahcf->dtb_compatible = "arm,arm-v8";
>
> + err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
> + ARM64_SYS_REG(3, 0, 0, 4, 0));
> + if (unlikely(err < 0)) {
> + /*
> + * Before v4.15, the kernel only exposed a limited number of system
> + * registers, not including any of the interesting AArch64 ID regs.
> + * For the most part we could leave these fields as zero with minimal
> + * effect, since this does not affect the values seen by the guest.
These older kernels do implement reading of id_isar0 through
id_isar5, though -- we could read and use those values rather than
leaving them zero.
> + *
> + * However, it could cause problems down the line for QEMU,
> + * so provide a minimal v8.0 default.
> + *
> + * ??? Could read MIDR and use knowledge from cpu64.c.
> + * ??? Could map a page of memory into our temp guest and
> + * run the tiniest of hand-crafted kernels to extract
> + * the values seen by the guest.
> + * ??? Either of these sounds like too much effort just
> + * to work around running a modern host kernel.
> + */
> + ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
> + err = 0;
Doesn't this code path leave everything except id_aa64pfr0 as
zero, thus leaving us with the "could cause problems down the
line" situation ?
thanks
-- PMM
