On 03/06/2011 12:06 PM, Jan Kiszka wrote:
In the system we model, the PIT is part of the PIIX3. The right way to
model it is as a DeviceState that's no_user=1 and created as part of the
initialized of PIIX3 (for the PC at least).
LPC is still an expansion bus and it's primarily used for discrete
components like a TPM. For components that are all part of a Super I/O
chip, there really just isn't a bus in the middle.
There surely is some bus (or even multiple), just not external an one.
It almost doesn't matter. It would look like:
I8254 is-a DeviceState
SuperIO has-a I8254
And the has-a relationship might be some custom bus mechanism (even if
it's purely a VHDL or software concept).
But in terms of modelling, we make I8254 a DeviceState because we don't
care what bus it sits on.
Most of the currently ISA-attached devices are chipset internal.
Yeah, and making them ISA devices was the wrong thing to do. This is
all going to have to be redone in the not too distant future.
An is-a relationship only makes sense when the device is naturally
represented as the parent object.
They
belong to the PIIX3, so they need to be attached to some bus that is
owned by this device. If that is its ISA bus or a separate one for
internal devices - really, this looks like an academic discussion to me.
It's far from academic as this is user-visible and visible via the
command line.
Regards,
Anthony Liguori
Jan