Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [RFC v2 00/24] Add RISC-V TCG backend support
Message-id: cover.1543352682.git.alistair.fran...@wdc.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
cb74f20 WIP: Try to patch longer branches
0b243f3 WIP: Add missing instructions
1a59fbe configure: Add support for building RISC-V host
e71f57d dias: Add RISC-V support
e4dea4c tcg: Add RISC-V cpu signal handler
24aab07 riscv: tcg-target: Add the target init code
1e0bb1f riscv: tcg-target: Add the prologue generation and register the JIT
5010323 riscv: tcg-target: Add the out op decoder
1aafad6 riscv: tcg-target: Add direct load and store instructions
80b4e55 riscv: tcg-target: Add slowpath load and store instructions
b4cb573 riscv: tcg-target: Add branch and jump instructions
ef58ab4 riscv: tcg-target: Add the out load and store instructions
b2ee4d7 riscv: tcg-target: Add the extract instructions
1b3b7a1 riscv: tcg-target: Add the mov and movi instruction
9836676 riscv: tcg-target: Add the relocation functions
a65fc9d riscv: tcg-target: Add the instruction emitters
73484d0 riscv: tcg-target: Add the immediate encoders
9d4b0a2 riscv: tcg-target: Add support for the constraints
70b78fc riscv: Add the tcg target registers
830a4b5 riscv: Add the tcg-target header file
049c426 exec: Add RISC-V GCC poison macro
60657c3 linux-user: Add host dependency for RISC-V 64-bit
463be15 linux-user: Add host dependency for RISC-V 32-bit
d6d6b1c elf.h: Add the RISCV ELF magic numbers
=== OUTPUT BEGIN ===
Checking PATCH 1/24: elf.h: Add the RISCV ELF magic numbers...
Checking PATCH 2/24: linux-user: Add host dependency for RISC-V 32-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12:
new file mode 100644
total: 0 errors, 1 warnings, 11 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/24: linux-user: Add host dependency for RISC-V 64-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12:
new file mode 100644
total: 0 errors, 1 warnings, 11 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/24: exec: Add RISC-V GCC poison macro...
Checking PATCH 5/24: riscv: Add the tcg-target header file...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11:
new file mode 100644
WARNING: architecture specific defines should be avoided
#43: FILE: tcg/riscv/tcg-target.h:28:
+#if __riscv_xlen == 32
total: 0 errors, 2 warnings, 173 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/24: riscv: Add the tcg target registers...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12:
new file mode 100644
total: 0 errors, 1 warnings, 116 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/24: riscv: tcg-target: Add support for the constraints...
Checking PATCH 8/24: riscv: tcg-target: Add the immediate encoders...
Checking PATCH 9/24: riscv: tcg-target: Add the instruction emitters...
Checking PATCH 10/24: riscv: tcg-target: Add the relocation functions...
Checking PATCH 11/24: riscv: tcg-target: Add the mov and movi instruction...
Checking PATCH 12/24: riscv: tcg-target: Add the extract instructions...
Checking PATCH 13/24: riscv: tcg-target: Add the out load and store
instructions...
Checking PATCH 14/24: riscv: tcg-target: Add branch and jump instructions...
Checking PATCH 15/24: riscv: tcg-target: Add slowpath load and store
instructions...
WARNING: line over 80 characters
#161: FILE: tcg/riscv/tcg-target.inc.c:893:
+ * see:
https://lists.nongnu.org/archive/html/qemu-devel/2018-11/msg02234.html
total: 0 errors, 1 warnings, 250 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 16/24: riscv: tcg-target: Add direct load and store
instructions...
ERROR: spaces required around that '*' (ctx:WxV)
#87: FILE: tcg/riscv/tcg-target.inc.c:1044:
+ tcg_insn_unit *label_ptr[1];
^
ERROR: spaces required around that '*' (ctx:WxV)
#158: FILE: tcg/riscv/tcg-target.inc.c:1115:
+ tcg_insn_unit *label_ptr[1];
^
total: 2 errors, 0 warnings, 178 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 17/24: riscv: tcg-target: Add the out op decoder...
Checking PATCH 18/24: riscv: tcg-target: Add the prologue generation and
register the JIT...
Checking PATCH 19/24: riscv: tcg-target: Add the target init code...
Checking PATCH 20/24: tcg: Add RISC-V cpu signal handler...
Checking PATCH 21/24: dias: Add RISC-V support...
Checking PATCH 22/24: configure: Add support for building RISC-V host...
Checking PATCH 23/24: WIP: Add missing instructions...
WARNING: line over 80 characters
#62: FILE: tcg/riscv/tcg-target.inc.c:654:
+ tcg_out_opc_reg(s, OPC_SLLI, TCG_REG_TMP0, rl, (rl == bl ? al :
bl));
total: 0 errors, 1 warnings, 113 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 24/24: WIP: Try to patch longer branches...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-de...@redhat.com
