This patch set adds RISC-V backend support to QEMU. This is based on Michael Clark's original work with extra work ontop.
This has been somewhat tested and can run other architecture softmmu code. It seems like any OS will eventually hang, but we can run the BIOS and OS startup code for a number of different operating systems. I haven't tested linux user support at all yet. I think Michael had that working reliably though and hopefully my changes haven't broken it. I'll have to test it before I send a full patchset. There are still some todos in the code (there are missing instructions and byte swapping). I think this series will have to be rebased ontop of Richard's TCG work before merging (although maybe we can get this in and then work on the rebase). This branch can be found here: https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend-upstream.next The working version with Michael's orignal patch and work ontop can be found here: https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend.next RFC v3: - Update the MAINTAINERS file - Enusre that RISC-V 32-bit works - More changes based on Richard's feedback and contributions RFC v2: - A large number of changes based on Richard's feedback Alistair Francis (24): elf.h: Add the RISCV ELF magic numbers linux-user: Add host dependency for RISC-V 32-bit linux-user: Add host dependency for RISC-V 64-bit linux-user: riscv: Fix compile failure on riscv32 hosts exec: Add RISC-V GCC poison macro riscv: Add the tcg-target header file riscv: Add the tcg target registers riscv: tcg-target: Add support for the constraints riscv: tcg-target: Add the immediate encoders riscv: tcg-target: Add the instruction emitters riscv: tcg-target: Add the relocation functions riscv: tcg-target: Add the mov and movi instruction riscv: tcg-target: Add the extract instructions riscv: tcg-target: Add the out load and store instructions riscv: tcg-target: Add the add2 and sub2 instructions riscv: tcg-target: Add branch and jump instructions riscv: tcg-target: Add slowpath load and store instructions riscv: tcg-target: Add direct load and store instructions riscv: tcg-target: Add the out op decoder riscv: tcg-target: Add the prologue generation and register the JIT riscv: tcg-target: Add the target init code tcg: Add RISC-V cpu signal handler dias: Add RISC-V support configure: Add support for building RISC-V host MAINTAINERS | 3 + accel/tcg/user-exec.c | 75 ++ configure | 12 +- disas.c | 10 +- include/elf.h | 55 + include/exec/poison.h | 1 + linux-user/host/riscv32/hostdep.h | 11 + linux-user/host/riscv64/hostdep.h | 11 + linux-user/riscv/target_syscall.h | 5 + tcg/riscv/tcg-target.h | 175 +++ tcg/riscv/tcg-target.inc.c | 1927 +++++++++++++++++++++++++++++ 11 files changed, 2281 insertions(+), 4 deletions(-) create mode 100644 linux-user/host/riscv32/hostdep.h create mode 100644 linux-user/host/riscv64/hostdep.h create mode 100644 tcg/riscv/tcg-target.h create mode 100644 tcg/riscv/tcg-target.inc.c -- 2.19.1