On 12/7/18 2:56 AM, Mark Cave-Ayland wrote:
> Instead of accessing the FPR, VMX and VSX registers through static arrays of
> TCGv_i64 globals, remove them and change the helpers to load/store data
> directly
> within cpu_env.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
> ---
> target/ppc/translate.c | 59
> ++++++++++++++------------------------------------
> 1 file changed, 16 insertions(+), 43 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Note however, that there are other steps that you must add here before using
vector operations in the next patch:
(1a) The fpr and vsr arrays must be merged, since fpr[n] == vsrh[n].
If this isn't done, then you simply cannot apply one operation
to two disjoint memory blocks.
(1b) The vsr and avr arrays should be merged, since vsr[32+n] == avr[n].
This is simply tidiness, matching the layout to the architecture.
These steps will modify gdbstub.c, machine.c, and linux-user/.
(2) The vsr array needs to be QEMU_ALIGN(16). See target/arm/cpu.h.
We assert that the host addresses are 16 byte aligned, so that we
can eventually use Altivec/VSX in tcg/ppc/.
r~
