The ARM PMU implementation currently contains a basic cycle counter, but it is often useful to gather counts of other events, filter them based on execution mode, and/or be notified on counter overflow. These patches flesh out the implementations of various PMU registers including PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent arbitrary counter types, implement mode filtering, send interrupts on counter overflow, and add instruction, cycle, and software increment events.
Since v9 [1] I have made the following changes: * Added a clarifying comment about how the PMU timer's migration is handled * Added a check against implementing PMCEID[23] if ID_DFR0.PerfMon == 0xf * Added TRACEFILT to the ID_DFR0 field definitions [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg00805.html Aaron Lindsay (14): migration: Add post_save function to VMStateDescription target/arm: Reorganize PMCCNTR accesses target/arm: Swap PMU values before/after migrations target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Allow AArch32 access for PMCCFILTR target/arm: Implement PMOVSSET target/arm: Define FIELDs for ID_DFR0 target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: PMU: Add instruction and cycle events target/arm: PMU: Set PMCR.N to 4 target/arm: Implement PMSWINC target/arm: Send interrupts on PMU counter overflow docs/devel/migration.rst | 9 +- include/migration/vmstate.h | 1 + migration/vmstate.c | 13 +- target/arm/cpu.c | 28 +- target/arm/cpu.h | 81 +++- target/arm/cpu64.c | 4 - target/arm/helper.c | 808 ++++++++++++++++++++++++++++++++---- target/arm/machine.c | 24 ++ 8 files changed, 863 insertions(+), 105 deletions(-) -- 2.19.2