On 2011-03-11 20:09, Jordan Justen wrote: > On Thu, Mar 10, 2011 at 16:27, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2...@gmx.net> wrote: >> Auf 11.03.2011 01:19, Jan Kiszka schrieb: >>> At least it's an in-band interface, which is the better choice as we >>> currently only have a PIIX3 southbridge for x86, predating even FWHs. >>> >> >> Right, that pretty much kills the option of using SPI unless someone >> wants to emulate a flash translation controller (e.g. the ITE IT8716F >> Super I/O). Can be done, would work, but the IT8716F has some quirks >> (max 1 MB SPI flash chips) which make it a less desirable option for >> emulation. > > I don't much like this, but we might consider adding the SPI host > controller MMIO just below the flash data. For the firmware, we > usually will know the size of firmware device that we've built for. > It seems SPI flash is pretty common today, and it sounds like > Carl-Daniel may have some SPI emulation code.
We don't emulate a chipset yet that includes SPI. Adding an artificial SPI master is like PV - the guests will require special drivers. > > Am I understanding correctly that CFI is programmed via MMIO in the > flash memory space? How difficult would it be to emulate CFI? Does Check qemu/hw/pflash_cfi02.c. > CFI have the same power-of-2 size flexibility as SPI? Yes. Jan
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