On Fri, 4 Jan 2019 at 14:29, Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > > From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and: > > 7. System Control > 7.1. Overview > > A10 embeds a high-speed SRAM which has been split into five segments. > See detailed memory mapping in following table: > > Area Address Size (Bytes) > A1 0x00000000-0x00003FFF 16K > A2 0x00004000-0x00007FFF 16K > A3 0x00008000-0x0000B3FF 13K > A4 0x0000B400-0x0000BFFF 3K > > Since for emulation purpose we don't need the segmentations, we simply define > the 'A' area as a single 48KB SRAM. > > We don't implement the following others areas: > - 'B': 'Secure RAM' (64K), > - 'C': Debug/ISP SRAM > - 'D': USB SRAM > > (qemu) info mtree > address-space: memory > 0000000000000000-ffffffffffffffff (prio 0, i/o): system > 0000000000000000-000000000000bfff (prio 0, ram): sram A > 0000000001c00000-0000000001c00fff (prio -1000, i/o): a10-sram-ctrl > 0000000001c0b000-0000000001c0bfff (prio 0, i/o): aw_emac > 0000000001c18000-0000000001c18fff (prio 0, i/o): ahci > 0000000001c18080-0000000001c180ff (prio 0, i/o): allwinner-ahci > 0000000001c20400-0000000001c207ff (prio 0, i/o): allwinner-a10-pic > 0000000001c20c00-0000000001c20fff (prio 0, i/o): allwinner-A10-timer > 0000000001c28000-0000000001c2801f (prio 0, i/o): serial > 0000000040000000-0000000047ffffff (prio 0, ram): cubieboard.ram > > Reported-by: Charlie Smurthwaite <charlie@atech.media> > Tested-by: Charlie Smurthwaite <charlie@atech.media> > Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> > --- > v2: Set owner=SoC in memory_region_init_ram() to avoid leak > when SoC is destroyed (Peter Maydell)
Applied to target-arm.next, thanks. -- PMM