On Tue, Jan 22, 2019 at 1:49 AM Bastian Koppelmann <kbast...@mail.uni-paderborn.de> wrote: > > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> > Signed-off-by: Peer Adelt <peer.ad...@hni.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/insn32-64.decode | 6 +++ > target/riscv/insn_trans/trans_rvf.inc.c | 54 +++++++++++++++++++++++++ > 2 files changed, 60 insertions(+) > > diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode > index 0bee95c984..6319f872ac 100644 > --- a/target/riscv/insn32-64.decode > +++ b/target/riscv/insn32-64.decode > @@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st > amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st > amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st > amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st > + > +# *** RV64F Standard Extension (in addition to RV32F) *** > +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm > +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm > +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm > +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm > diff --git a/target/riscv/insn_trans/trans_rvf.inc.c > b/target/riscv/insn_trans/trans_rvf.inc.c > index b101593ac4..b667c576d4 100644 > --- a/target/riscv/insn_trans/trans_rvf.inc.c > +++ b/target/riscv/insn_trans/trans_rvf.inc.c > @@ -332,3 +332,57 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x > *a) > > return true; > } > + > +#ifdef TARGET_RISCV64 > +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); > + gen_set_gpr(a->rd, t0); > + tcg_temp_free(t0); > + return true; > +} > + > +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); > + gen_set_gpr(a->rd, t0); > + tcg_temp_free(t0); > + return true; > +} > + > +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_get_gpr(t0, a->rs1); > + > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); > + > + tcg_temp_free(t0); > + return true; > +} > + > +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) > +{ > + REQUIRE_FPU; > + > + TCGv t0 = tcg_temp_new(); > + gen_get_gpr(t0, a->rs1); > + > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); > + > + tcg_temp_free(t0); > + return true; > +} > +#endif > -- > 2.20.1 > >