Re: [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G()

[Alistair]

On 1/23/19 1:25 AM, Bastian Koppelmann wrote:

decodetree handles all instructions now so the fallback is not necessary
anymore.

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.ad...@hni.uni-paderborn.de>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

---
  target/riscv/translate.c | 23 +----------------------
  1 file changed, 1 insertion(+), 22 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0e37beb68e..b0251b3518 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -600,26 +600,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
  #include "decode_insn16.inc.c"
  #include "insn_trans/trans_rvc.inc.c"

-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)

-{
-    uint32_t op;
-
-    /* We do not do misaligned address check here: the address should never be
-     * misaligned at this point. Instructions that set PC must do the check,
-     * since epc must be the address of the instruction that caused us to
-     * perform the misaligned instruction fetch */
-
-    op = MASK_OP_MAJOR(ctx->opcode);
-
-    switch (op) {
-    case OPC_RISC_SYSTEM:
-        break;
-    default:
-        gen_exception_illegal(ctx);
-        break;
-    }
-}
-
  static void decode_opc(DisasContext *ctx)
  {
      /* check for compressed insn */
@@ -636,8 +616,7 @@ static void decode_opc(DisasContext *ctx)
      } else {
          ctx->pc_succ_insn = ctx->base.pc_next + 4;
          if (!decode_insn32(ctx, ctx->opcode)) {
-            /* fallback to old decoder */
-            decode_RV32_64G(ctx->env, ctx);
+            gen_exception_illegal(ctx);
          }
      }
  }