On 1/21/19 10:51 AM, Peter Maydell wrote: > The SSE-200 has 4 banks of SRAM, each with its own internal > Memory Protection Controller. The interrupt status for these > extra MPCs appears in the same security controller SECMPCINTSTATUS > register as the MPC for the IoTKit's single SRAM bank. Enhance the > iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE > variant in use does not have all 4 MPCs then the unused inputs will > simply result in the SECMPCINTSTATUS bits being zero as required.) > > The hardcoded constant "1"s in armsse.c indicate the actual number > of SRAM MPCs the IoTKit has, and will be replaced in the following > commit. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > include/hw/misc/iotkit-secctl.h | 6 +++--- > hw/arm/armsse.c | 6 +++--- > hw/misc/iotkit-secctl.c | 5 +++-- > 3 files changed, 9 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
