On Fri, Jan 25, 2019 at 7:26 PM Peter Maydell <peter.mayd...@linaro.org> wrote: > > In the AdvSIMD scalar x indexed element and vector x indexed element > encoding group, the SDOT and UDOT instructions are vector only, > and their opcode is unallocated in the scalar group. Correctly > UNDEF this unallocated encoding. > > Reported-by: Laurent Desnogues <laurent.desnog...@gmail.com> > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnog...@gmail.com> Thanks, Laurent > --- > target/arm/translate-a64.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 474d9bfb5f0..30bc2412fc0 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -12641,7 +12641,7 @@ static void disas_simd_indexed(DisasContext *s, > uint32_t insn) > break; > case 0x0e: /* SDOT */ > case 0x1e: /* UDOT */ > - if (size != MO_32 || !dc_isar_feature(aa64_dp, s)) { > + if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) { > unallocated_encoding(s); > return; > } > -- > 2.20.1 >