On Thu, 24 Jan 2019 at 14:08, Cédric Le Goater <c...@kaod.org> wrote: > > Hello, > > When in the User command mode, the Aspeed SMC controller driver > performs the dummy cycles of a fast read command using byte transfers, > that is ony byte for eight cycles. But, the QEMU m25p80 models one > dummy cycle with one byte transfer. > > To restore the correct number of cycles, this series adds a function > snooping the SPI transfers to catch commands requiring dummy cycles > and replaces them with byte transfers compatible with the m25p80 model. > > Thanks, > > C. > > Cédric Le Goater (4): > aspeed/smc: fix default read value > aspeed/smc: define registers for all possible CS > aspeed/smc: Add dummy data register > aspeed/smc: snoop transfers to fake dummy cycles
Applied to target-arm.next, thanks. -- PMM