It looks like this is fixed as of c7b951718815 ("RISC-V: Implement
modular CSR helper interface"), which was merged on January 14th.-- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1815078 Title: Qemu 3.1.0 risc-v mie.MEIE Status in QEMU: New Bug description: Hello all, There is a bug in qemu for Risc-v, related to the mie register: when we try to set the MEIE bit (11) nothing is done, even when we are running at machine mode. Li a0 , 1 << 11 Csrs mie , a0 And when we read mie it is as though nothing was done. Going through the qemu source code I was able to correct it: on file op_helper.c, line 94, the variable all_ints should be initialized with: uint64_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP | MIP_MEIP; That is, the MIP_MEIP was missing. I've successfully triggered uart interrupts with this patch (virt machine). All the best, Pharos team To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1815078/+subscriptions
