Patchew URL: https://patchew.org/QEMU/20190214190603.25030-1-peter.mayd...@linaro.org/
Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20190214190603.25030-1-peter.mayd...@linaro.org Subject: [Qemu-devel] [PULL 00/27] target-arm queue Type: series === TEST SCRIPT BEGIN === #!/bin/bash git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' fb39c2e90f gdbstub: Send a reply to the vKill packet. 86563bda9d target/arm: Add missing clear_tail calls 866f1958b4 target/arm: Use vector operations for saturation 7fadd905a7 target/arm: Split out FPSCR.QC to a vector field 3bbf4384f9 target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] 178fe16ac8 target/arm: Split out flags setting from vfp compares 1fb9548fec target/arm: Fix arm_cpu_dump_state vs FPSCR c045bbe35f target/arm: Fix vfp_gdb_get/set_reg vs FPSCR 0bfb764ba7 target/arm: Remove neon min/max helpers 4a40d71633 target/arm: Use tcg integer min/max primitives for neon 9eaba50860 target/arm: Use vector minmax expanders for aarch32 e222548533 target/arm: Use vector minmax expanders for aarch64 e77230191f target/arm: Rely on optimization within tcg_gen_gvec_or 3f7cda73b2 hw/arm/armsse: Fix miswiring of expansion IRQs d93ebe8185 hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 cce31aab3d MAINTAINERS: Remove Peter Crosthwaite from various entries 9891e5f6c7 arm: Allow system registers for KVM guests to be changed by QEMU code ab703f0d5a linux-user/elfload: enable HWCAP_CPUID for AArch64 b4301eab08 target/arm: expose remaining CPUID registers as RAZ 7abf3c8631 target/arm: expose MPIDR_EL1 to userspace d17bc752d8 target/arm: expose CPUID registers to userspace 721d2c2056 target/arm: relax permission checks for HWCAP_CPUID registers 70d62fd729 target/arm: Restructure disas_fp_int_conv 907d999506 target/arm: Force result size into dp after operation a20dcecfa6 target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be d42d84b7b1 target/arm: Implement HACR_EL2 f1dfc8484b target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR === OUTPUT BEGIN === 1/27 Checking commit f1dfc8484bc4 (target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR) 2/27 Checking commit d42d84b7b110 (target/arm: Implement HACR_EL2) 3/27 Checking commit a20dcecfa649 (target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be) 4/27 Checking commit 907d99950666 (target/arm: Force result size into dp after operation) 5/27 Checking commit 70d62fd72937 (target/arm: Restructure disas_fp_int_conv) 6/27 Checking commit 721d2c20567e (target/arm: relax permission checks for HWCAP_CPUID registers) 7/27 Checking commit d17bc752d844 (target/arm: expose CPUID registers to userspace) 8/27 Checking commit 7abf3c863143 (target/arm: expose MPIDR_EL1 to userspace) 9/27 Checking commit b4301eab085b (target/arm: expose remaining CPUID registers as RAZ) 10/27 Checking commit ab703f0d5a46 (linux-user/elfload: enable HWCAP_CPUID for AArch64) 11/27 Checking commit 9891e5f6c709 (arm: Allow system registers for KVM guests to be changed by QEMU code) 12/27 Checking commit cce31aab3d66 (MAINTAINERS: Remove Peter Crosthwaite from various entries) 13/27 Checking commit d93ebe8185a4 (hw/intc/armv7m_nvic: Allow byte accesses to SHPR1) 14/27 Checking commit 3f7cda73b20a (hw/arm/armsse: Fix miswiring of expansion IRQs) 15/27 Checking commit e77230191f43 (target/arm: Rely on optimization within tcg_gen_gvec_or) 16/27 Checking commit e222548533b0 (target/arm: Use vector minmax expanders for aarch64) 17/27 Checking commit 9eaba5086098 (target/arm: Use vector minmax expanders for aarch32) 18/27 Checking commit 4a40d7163314 (target/arm: Use tcg integer min/max primitives for neon) 19/27 Checking commit 0bfb764ba772 (target/arm: Remove neon min/max helpers) 20/27 Checking commit c045bbe35fd4 (target/arm: Fix vfp_gdb_get/set_reg vs FPSCR) ERROR: trailing statements should be on next line #25: FILE: target/arm/helper.c:84: + case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; ERROR: trailing statements should be on next line #34: FILE: target/arm/helper.c:110: + case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; total: 2 errors, 0 warnings, 16 lines checked Patch 20/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 21/27 Checking commit 1fb9548fec41 (target/arm: Fix arm_cpu_dump_state vs FPSCR) 22/27 Checking commit 178fe16ac872 (target/arm: Split out flags setting from vfp compares) 23/27 Checking commit 3bbf4384f995 (target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]) 24/27 Checking commit 7fadd905a7f3 (target/arm: Split out FPSCR.QC to a vector field) 25/27 Checking commit 866f1958b4d7 (target/arm: Use vector operations for saturation) ERROR: spaces required around that '*' (ctx:WxV) #360: FILE: target/arm/vec_helper.c:774: + TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ ^ total: 1 errors, 0 warnings, 438 lines checked Patch 25/27 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 26/27 Checking commit 86563bda9da9 (target/arm: Add missing clear_tail calls) 27/27 Checking commit fb39c2e90f66 (gdbstub: Send a reply to the vKill packet.) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190214190603.25030-1-peter.mayd...@linaro.org/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-de...@redhat.com