Hello, Here is another series of fixes and extensions from Ben providing support for POWER9 native hash MMU and POWER9 native radix MMU. These prepare ground for the support of QEMU POWER9 PowerNV machines.
>From there, I hand over the patchset to Suraj for any follow-ups. Thanks, C. Benjamin Herrenschmidt (12): target/ppc/spapr: Set LPCR:HR when using Radix mode target/ppci/mmu: Use LPCR:HR to chose radix vs. hash translation target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors target/ppc: Fix #include guard in mmu-book3s-v3.h target/ppc: Cleanup 64-bit MMU includes target/ppc: Fix ordering of hash MMU accesses target/ppc: Add basic support for "new format" HPTE as found on POWER9 target/ppc: Fix synchronization of mttcg with broadcast TLB flushes target/ppc: Flush the TLB locally when the LPIDR is written target/ppc: Rename PATB/PATBE -> PATE target/ppc: Support for POWER9 native hash target/ppc: Basic POWER9 bare-metal radix MMU support include/hw/ppc/spapr.h | 1 + target/ppc/cpu.h | 7 ++- target/ppc/helper.h | 1 + target/ppc/helper_regs.h | 27 ++++------ target/ppc/mmu-book3s-v3.h | 89 +++++++++++++++++++++++++++--- target/ppc/mmu-hash64.h | 22 ++------ target/ppc/mmu-radix64.h | 4 +- hw/ppc/spapr.c | 86 ++++++++++++++++++++++++----- hw/ppc/spapr_hcall.c | 69 +++++++----------------- hw/ppc/spapr_rtas.c | 6 +-- target/ppc/misc_helper.c | 15 ++++++ target/ppc/mmu-book3s-v3.c | 31 +++++++++-- target/ppc/mmu-hash32.c | 6 +++ target/ppc/mmu-hash64.c | 28 ++++++++-- target/ppc/mmu-radix64.c | 96 ++++++++++++++++++++++++++------- target/ppc/mmu_helper.c | 9 +--- target/ppc/translate_init.inc.c | 7 ++- 17 files changed, 361 insertions(+), 143 deletions(-) -- 2.20.1
