On 3/3/19 9:23 AM, Mark Cave-Ayland wrote: > When VSX support was initially added, the fpr registers were added at > offset 0 of the VSR register and the vsrl registers were added at offset > 1. This is in contrast to the VMX registers (the last 32 VSX registers) which > are stored in host-endian order. > > Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also > stored in host endian order to match the VMX registers. This ensures that TCG > vector operations involving mixed VMX and VSX registers will function > correctly. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> > --- > target/ppc/cpu.h | 4 ++-- > target/ppc/internal.h | 8 ++++---- > target/ppc/machine.c | 8 ++++---- > 3 files changed, 10 insertions(+), 10 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
