From: Bin Meng <bmeng...@gmail.com> At present the sifive uart model only generates RX interrupt. This updates it to generate TX interrupt so that it is more useful.
Note the TX fifo is still unimplemented. Signed-off-by: Bin Meng <bmeng...@gmail.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> --- hw/riscv/sifive_uart.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index 456a3d3697c2..3b3f94f51ddf 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -51,7 +51,8 @@ static uint64_t uart_ip(SiFiveUARTState *s) static void update_irq(SiFiveUARTState *s) { int cond = 0; - if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) { + if ((s->ie & SIFIVE_UART_IE_TXWM) || + ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) { cond = 1; } if (cond) { @@ -108,6 +109,7 @@ uart_write(void *opaque, hwaddr addr, switch (addr) { case SIFIVE_UART_TXFIFO: qemu_chr_fe_write(&s->chr, &ch, 1); + update_irq(s); return; case SIFIVE_UART_IE: s->ie = val64; -- 2.19.2