From: Richard Henderson <richard.hender...@linaro.org>
We were using the wrong flush-to-zero bit for the non-half input.
Fixes: 46d33d1e3c9
Cc: qemu-sta...@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnog...@gmail.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnog...@gmail.com>
Tested-by: Laurent Desnogues <laurent.desnog...@gmail.com>
Message-id: 20180810193129.1556-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
(cherry picked from commit e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4)
Signed-off-by: Michael Roth <mdr...@linux.vnet.ibm.com>
---
target/arm/translate-sve.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index d27bc8c946..667879564f 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4093,7 +4093,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn,
int pg,
static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh);
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
}
static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
@@ -4103,7 +4103,7 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz
*a, uint32_t insn)
static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh);
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
}
static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
--
2.17.1
