On Wed, 3 Apr 2019 at 10:44, Richard Henderson
<richard.hender...@linaro.org> wrote:
> +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> + MMUAccessType access_type, int mmu_idx,
> + bool probe, uintptr_t retaddr)
> +{
> + ARMCPU *cpu = ARM_CPU(cs);
> +
> +#ifdef CONFIG_USER_ONLY
> + cpu->env.exception.vaddress = address;
> + if (access_type == MMU_INST_FETCH) {
> + cs->exception_index = EXCP_PREFETCH_ABORT;
> + } else {
> + cs->exception_index = EXCP_DATA_ABORT;
> + }
> + cpu_loop_exit_restore(cs, retaddr);
> +#else
> + hwaddr phys_addr;
> + target_ulong page_size;
> + int prot, ret;
> + MemTxAttrs attrs = {};
> + ARMMMUFaultInfo fi = {};
> +
> + /*
> + * Walk the page table and (if the mapping exists) add the page
> + * to the TLB. Return false on success, or true on failure. Populate
> + * fsr with ARM DFSR/IFSR fault register format value on failure.
> + */
This comment about what we return doesn't seem to match what
the code is doing.
thanks
-- PMM
