The following changes since commit 49fc899f8d673dd9e73f3db0d9e9ea60b77c331b:
Update version for v4.0.0-rc1 release (2019-03-26 17:02:29 +0000) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-rc3 for you to fetch changes up to b84ffcecdb7a6a3e9946d0d6d24703199c4880b3: riscv: plic: Log guest errors (2019-03-27 20:23:03 -0700) ---------------------------------------------------------------- RISC-V Patches for 4.0-rc3 This patch set contains a pair of tightly coupled PLIC bug fixes: * We were calculating the PLIC addresses incorrectly. * We were installing the wrong number of PLIC interrupts. The two bugs togther resulted in a mostly-working system, but they're impossible to seperate because fixing one bug would result in significant breakage. As a result they're in the same patch. There is also a cleanup to use qemu_log_mask(LOG_GUEST_ERROR,...) for error reporting. As far as I know these are the last outstanding RISC-V patches for 4.0. ---------------------------------------------------------------- Alistair Francis (2): riscv: plic: Fix incorrect irq calculation riscv: plic: Log guest errors hw/riscv/sifive_plic.c | 16 +++++++++++----- hw/riscv/sifive_u.c | 2 +- include/hw/riscv/sifive_e.h | 2 +- include/hw/riscv/sifive_u.h | 4 ++-- include/hw/riscv/virt.h | 2 +- 5 files changed, 16 insertions(+), 10 deletions(-)