> On Apr 10, 2019, at 16:01, Philippe Mathieu-Daudé <phi...@redhat.com> wrote:
>
> So your description and patch makes sens.
> What worries me is the controller could have other pending IRQs to
> deliver and you are clearing them. Shouldn't we only clear the
> INTR_TXINT bit, and call escc_update_irq() which should lower the IRQ if
> no bits are pending?
>
> Maybe as:
>
> s->wregs[W_INTR] &= ~INTR_TXINT;
> escc_update_irq(s);
I just sent a v2 patch (but it looks like I failed to include Philippe, sorry
about that!)
I used
s->txint = 0;
escc_update_irq(s);
which appears to do the right thing in my tests.
Thank you,
Steve
--
Stephen Checkoway
