On 4/16/19 5:57 AM, Peter Maydell wrote: > For M-profile the MVFR* ID registers are memory mapped, in the > range we implement via the NVIC. Allow them to be read. > (If the CPU has no FPU, these registers are defined to be RAZ.) > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > hw/intc/armv7m_nvic.c | 6 ++++++ > 1 file changed, 6 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
