Re: [Qemu-devel] [PATCH 2/2] target/riscv: Add checks for several RVC reserved operands

[Richard Henderson]

On 4/25/19 10:26 AM, Richard Henderson wrote:
>  {
> +  illegal         011 0  -----  00000 01 # c.addi16sp, RES nzimm=0
>    addi            011 .  00010  ..... 01 @c_addi16sp
>    lui             011 .  .....  ..... 01 @c_lui
>  }

Bah.  I just realized the comment should be more like

  # c.addi16sp and c.lui, RES nzimm=0

Otherwise one is led to believe that rd=2 is missing
from the illegal pattern.


r~