On Tue, May 07, 2019 at 10:48:06AM +1000, Anton Blanchard wrote: > During the conversion these instructions were incorrectly treated as > stores. We need to use set_cpu_vsr* and not get_cpu_vsr*. > > Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() > helpers for VSR register access") > Signed-off-by: Anton Blanchard <an...@ozlabs.org> > --- > target/ppc/translate/vsx-impl.inc.c | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/target/ppc/translate/vsx-impl.inc.c > b/target/ppc/translate/vsx-impl.inc.c > index 05b75105be..c13f84e745 100644 > --- a/target/ppc/translate/vsx-impl.inc.c > +++ b/target/ppc/translate/vsx-impl.inc.c > @@ -102,8 +102,7 @@ static void gen_lxvw4x(DisasContext *ctx) > } > xth = tcg_temp_new_i64(); > xtl = tcg_temp_new_i64(); > - get_cpu_vsrh(xth, xT(ctx->opcode)); > - get_cpu_vsrl(xtl, xT(ctx->opcode)); > +
Something seems amiss here. Clearly we do need a set..() back to the loaded register, but with the removal of these gets, it doesn't look like the xth and xtl temporaries are initialized any more. > gen_set_access_type(ctx, ACCESS_INT); > EA = tcg_temp_new(); > > @@ -126,6 +125,8 @@ static void gen_lxvw4x(DisasContext *ctx) > tcg_gen_addi_tl(EA, EA, 8); > tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); > } > + set_cpu_vsrh(xT(ctx->opcode), xth); > + set_cpu_vsrl(xT(ctx->opcode), xtl); > tcg_temp_free(EA); > tcg_temp_free_i64(xth); > tcg_temp_free_i64(xtl); > @@ -185,8 +186,6 @@ static void gen_lxvh8x(DisasContext *ctx) > } > xth = tcg_temp_new_i64(); > xtl = tcg_temp_new_i64(); > - get_cpu_vsrh(xth, xT(ctx->opcode)); > - get_cpu_vsrl(xtl, xT(ctx->opcode)); > gen_set_access_type(ctx, ACCESS_INT); > > EA = tcg_temp_new(); > @@ -197,6 +196,8 @@ static void gen_lxvh8x(DisasContext *ctx) > if (ctx->le_mode) { > gen_bswap16x8(xth, xtl, xth, xtl); > } > + set_cpu_vsrh(xT(ctx->opcode), xth); > + set_cpu_vsrl(xT(ctx->opcode), xtl); > tcg_temp_free(EA); > tcg_temp_free_i64(xth); > tcg_temp_free_i64(xtl); > @@ -214,14 +215,14 @@ static void gen_lxvb16x(DisasContext *ctx) > } > xth = tcg_temp_new_i64(); > xtl = tcg_temp_new_i64(); > - get_cpu_vsrh(xth, xT(ctx->opcode)); > - get_cpu_vsrl(xtl, xT(ctx->opcode)); > gen_set_access_type(ctx, ACCESS_INT); > EA = tcg_temp_new(); > gen_addr_reg_index(ctx, EA); > tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ); > tcg_gen_addi_tl(EA, EA, 8); > tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); > + set_cpu_vsrh(xT(ctx->opcode), xth); > + set_cpu_vsrl(xT(ctx->opcode), xtl); > tcg_temp_free(EA); > tcg_temp_free_i64(xth); > tcg_temp_free_i64(xtl); -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
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