On 5/17/19 6:51 AM, Richard Henderson wrote: > This is Sato-san's v13, plus the typos that Phil noticed therein, > plus the change to tlb_fill required by > > commit d8276573da58e8ce78dab8c46dd660efd664bcb7 > Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' > Add CPUClass::tlb_fill. > Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. > > > r~ > > > Richard Henderson (1): > target/rx: Convert to CPUClass::tlb_fill > > Yoshinori Sato (12): > target/rx: TCG translation > target/rx: TCG helper > target/rx: CPU definition > target/rx: RX disassembler > hw/intc: RX62N interrupt controller (ICUa) > hw/timer: RX62N internal timer modules > hw/char: RX62N serial communication interface (SCI) > hw/rx: RX Target hardware definition > qemu/bitops.h: Add extract8 and extract16 > hw/registerfields.h: Add 8bit and 16bit register macros > Add rx-softmmu > MAINTAINERS: Add RX
Series: Tested-by: Philippe Mathieu-Daudé <phi...@redhat.com> But please reorder patches before sending the pull request, see: https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg03671.html - patch 9 first "Add extract8 and extract16" - patch 10 then "Add 8bit and 16bit register macros" - then other patches 1-8, 11-13 This will help if we unlikely have to bisect ;) Regards, Phil.
