On Wed, May 29, 2019 at 01:16:52PM +0200, Igor Mammedov wrote: > On Tue, 28 May 2019 22:43:31 +0200 > Gerd Hoffmann <kra...@redhat.com> wrote: > > > This patch changes the handling of the mmconfig area. Thanks to the > > pci(e) expander devices we already have the logic to exclude address > > ranges from PCI0._CRS. We can simply add the mmconfig address range > > to the list get it excluded as well. > > > > With that in place we can go with a fixed pci hole which covers the > > whole area from the end of (low) ram to the ioapic. > > > > This will make the whole logic alot less fragile. No matter where the > > firmware places the mmconfig xbar, things should work correctly. The > > guest also gets a bit more PCI address space (seabios boot): > > > > # cat /proc/iomem > > [ ... ] > > 7ffdd000-7fffffff : reserved > > 80000000-afffffff : PCI Bus 0000:00 <<-- this is new > > b0000000-bfffffff : PCI MMCONFIG 0000 [bus 00-ff] > > b0000000-bfffffff : reserved > > c0000000-febfffff : PCI Bus 0000:00 > > f8000000-fbffffff : 0000:00:01.0 > > [ ... ] > > > > So this is a guest visible change. > > My impression was that QEMU would/should add into CRS whatever bars > firmware programmed (and it looks like QEMU doesn't do it right).
Well, that works reasonable well. It looks at all pci bars. The ones which do not belong to PCI0 are added to their pci(e) expander. All remaining address space of the pci hole is added to PCI0. At times things look a bit odd as all unused ranges go to PCI0 even in cases like this one: [ ... ] 84a00000-85203fff : PCI Bus 0000:40 84a00000-84bfffff : PCI Bus 0000:44 84c00000-84dfffff : PCI Bus 0000:43 84e00000-84ffffff : PCI Bus 0000:42 85000000-851fffff : PCI Bus 0000:41 85200000-85200fff : 0000:40:02.3 85201000-85201fff : 0000:40:02.2 85202000-85202fff : 0000:40:02.1 85203000-85203fff : 0000:40:02.0 85204000-853fffff : PCI Bus 0000:00 <<-- this could be given to PCI Bus 0000:40 85400000-85c03fff : PCI Bus 0000:80 85400000-855fffff : PCI Bus 0000:84 [ ... ] but that is more or less cosmetical. > So I'm not really fond of adding bigger hole just to paper over > existing bug (still might be the way to go). Let me ponder a bit > on it and look into what's isn't working on QEMU side properly. Basically qemu assumes the (32bit) pci hole starts above the mmconfig bar. The pci hole should start above low memory though, like it does on 'pc'. And the mmconfig bar should be excluded. cheers, Gerd
