On Tue, 18 Jun 2019 at 16:54, Cédric Le Goater <c...@kaod.org> wrote: > > From: Andrew Jeffery <and...@aj.id.au> > > From the datasheet: > > This register stores the current status of counter #N. When timer > enable bit TMC30[N * b] is disabled, the reload register will be > loaded into this counter. When timer bit TMC30[N * b] is set, the > counter will start to decrement. CPU can update this register value > when enable bit is set. > > Signed-off-by: Andrew Jeffery <and...@aj.id.au> > Signed-off-by: Cédric Le Goater <c...@kaod.org>
Reviewed-by: Joel Stanley <j...@jms.id.au>
