Add all SSE2 instructions to the x86 configuration file. Signed-off-by: Jan Bobek <jan.bo...@gmail.com> --- x86.risu | 160 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 153 insertions(+), 7 deletions(-)
diff --git a/x86.risu b/x86.risu index cc40bbc..b3e4c88 100644 --- a/x86.risu +++ b/x86.risu @@ -12,63 +12,137 @@ # Input file for risugen defining x86 instructions .mode x86 -# SSE Data Transfer Instructions +# SSE/SSE2 Data Transfer Instructions MOVUPS SSE 00001111 0001000 d !emit { modrm(); mem(size => 16); } +MOVUPD SSE2 00001111 0001000 d !emit { data16(); modrm(); mem(size => 16); } MOVSS SSE 00001111 0001000 d !emit { rep(); modrm(); mem(size => 4); } +MOVSD SSE2 00001111 0001000 d !emit { repne(); modrm(); mem(size => 8); } + MOVHLPS SSE 00001111 00010010 !emit { modrm(mod => MOD_DIRECT); } MOVLPS SSE 00001111 0001001 d !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); } +MOVLPD SSE2 00001111 0001001 d !emit { data16(); modrm(mod => ~MOD_DIRECT); mem(size => 8); } + MOVLHPS SSE 00001111 00010110 !emit { modrm(mod => MOD_DIRECT); } MOVHPS SSE 00001111 0001011 d !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); } +MOVHPD SSE2 00001111 0001011 d !emit { data16(); modrm(mod => ~MOD_DIRECT); mem(size => 8); } + MOVAPS SSE 00001111 0010100 d !emit { modrm(); mem(size => 16, align => 16); } +MOVAPD SSE2 00001111 0010100 d !emit { data16(); modrm(); mem(size => 16, align => 16); } + MOVMSKPS SSE 00001111 01010000 !emit { modrm(mod => MOD_DIRECT, reg => ~REG_ESP); } +MOVMKSPD SSE2 00001111 01010000 !emit { data16(); modrm(mod => MOD_DIRECT, reg => ~REG_ESP); } -# SSE Packed Arithmetic Instructions +# SSE/SSE2 Packed Arithmetic Instructions ADDPS SSE 00001111 01011000 !emit { modrm(); mem(size => 16, align => 16); } +ADDPD SSE2 00001111 01011000 !emit { data16(); modrm(); mem(size => 16, align => 16) } ADDSS SSE 00001111 01011000 !emit { rep(); modrm(); mem(size => 4); } +ADDSD SSE2 00001111 01011000 !emit { repne(); modrm(); mem(size => 4); } + SUBPS SSE 00001111 01011100 !emit { modrm(); mem(size => 16, align => 16); } +SUBPD SSE2 00001111 01011100 !emit { data16(); modrm(); mem(size => 16, align => 16); } SUBSS SSE 00001111 01011100 !emit { rep(); modrm(); mem(size => 4); } +SUBSD SSE2 00001111 01011100 !emit { repne(); modrm(); mem(size => 4); } + MULPS SSE 00001111 01011001 !emit { modrm(); mem(size => 16, align => 16); } +MULPD SSE2 00001111 01011001 !emit { data16(); modrm(); mem(size => 16, align => 16); } MULSS SSE 00001111 01011001 !emit { rep(); modrm(); mem(size => 4); } -DIVPS SSE 00001111 01011110 !emit { modrm(); mem(size => 16, align => 16); } +MULSD SSE2 00001111 01011001 !emit { repne(); modrm(); mem(size => 4); } + +DIVPS SSE 00001111 01011110 !emit { modrm(); modrm(); mem(size => 16, align => 16); } +DIVPD SSE2 00001111 01011110 !emit { data16(); modrm(); mem(size => 16, align => 16); } DIVSS SSE 00001111 01011110 !emit { rep(); modrm(); mem(size => 4); } +DIVSD SSE2 00001111 01011110 !emit { repne(); modrm(); mem(size => 4); } + RCPPS SSE 00001111 01010011 !emit { modrm(); mem(size => 16, align => 16); } RCPSS SSE 00001111 01010011 !emit { rep(); modrm(); mem(size => 4); } + SQRTPS SSE 00001111 01010001 !emit { modrm(); mem(size => 16, align => 16); } +SQRTPD SSE2 00001111 01010001 !emit { data16(); modrm(); mem(size => 16, align => 16); } SQRTSS SSE 00001111 01010001 !emit { rep(); modrm(); mem(size => 4); } +SQRTSD SSE2 00001111 01010001 !emit { repne(); modrm(); mem(size => 4); } + RSQRTPS SSE 00001111 01010010 !emit { modrm(); mem(size => 16, align => 16); } RSQRTSS SSE 00001111 01010010 !emit { rep(); modrm(); mem(size => 4); } + MINPS SSE 00001111 01011101 !emit { modrm(); mem(size => 16, align => 16); } +MINPD SSE2 00001111 01011101 !emit { data16(); modrm(); mem(size => 16, align => 16); } MINSS SSE 00001111 01011101 !emit { rep(); modrm(); mem(size => 4); } +MINSD SSE2 00001111 01011101 !emit { repne(); modrm(); mem(size => 4); } + MAXPS SSE 00001111 01011111 !emit { modrm(); mem(size => 16, align => 16); } +MAXPD SSE2 00001111 01011111 !emit { data16(); modrm(); mem(size => 16, align => 16); } MAXSS SSE 00001111 01011111 !emit { rep(); modrm(); mem(size => 4); } +MAXSD SSE2 00001111 01011111 !emit { repne(); modrm(); mem(size => 4); } -# SSE Comparison Instructions +# SSE/SSE2 Comparison Instructions CMPPS SSE 00001111 11000010 !emit { modrm(); mem(size => 16, align => 16); imm(size => 1); } +CMPPD SSE2 00001111 11000010 !emit { data16(); modrm(); mem(size => 16, align => 16); imm(size => 1); } CMPSS SSE 00001111 11000010 !emit { rep(); modrm(); mem(size => 4); imm(size => 1); } +CMPSD SSE2 00001111 11000010 !emit { repne(); modrm(); mem(size => 4); imm(size => 1); } + UCOMISS SSE 00001111 00101110 !emit { modrm(); mem(size => 4); } +UCOMISD SSE2 00001111 00101110 !emit { data16(); modrm(); mem(size => 4); } + COMISS SSE 00001111 00101111 !emit { modrm(); mem(size => 4); } +COMISD SSE2 00001111 00101111 !emit { data16(); modrm(); mem(size => 4); } -# SSE Logical Instructions +# SSE/SSE2 Logical Instructions ANDPS SSE 00001111 01010100 !emit { modrm(); mem(size => 16, align => 16); } +ANDPD SSE2 00001111 01010100 !emit { data16(); modrm(); mem(size => 16, align => 16); } + ANDNPS SSE 00001111 01010101 !emit { modrm(); mem(size => 16, align => 16); } +ANDNPD SSE2 00001111 01010101 !emit { data16(); modrm(); mem(size => 16, align => 16); } + ORPS SSE 00001111 01010110 !emit { modrm(); mem(size => 16, align => 16); } +ORPD SSE2 00001111 01010110 !emit { data16(); modrm(); mem(size => 16, align => 16); } + XORPS SSE 00001111 01010111 !emit { modrm(); mem(size => 16, align => 16); } +XORPD SSE2 00001111 01010111 !emit { data16(); modrm(); mem(size => 16, align => 16); } -# SSE Shuffle and Unpack Instructions +# SSE/SSE2 Shuffle and Unpack Instructions SHUFPS SSE 00001111 11000110 !emit { modrm(); mem(size => 16, align => 16); imm(size => 1); } +SHUFPD SSE2 00001111 11000110 !emit { data16(); modrm(); mem(size => 16, align => 16); imm(size => 1); } + UNPCKLPS SSE 00001111 00010100 !emit { modrm(); mem(size => 16, align => 16); } +UNPCKLPD SSE2 00001111 00010100 !emit { data16(); modrm(); mem(size => 16, align => 16); } + UNPCKHPS SSE 00001111 00010101 !emit { modrm(); mem(size => 16, align => 16); } +UNPCKHPD SSE2 00001111 00010101 !emit { data16(); modrm(); mem(size => 16, align => 16); } -# SSE Conversion Instructions +# SSE/SSE2 Conversion Instructions CVTPI2PS SSE 00001111 00101010 !emit { modrm(); mem(size => 8); } +CVTPI2PD SSE2 00001111 00101010 !emit { data16(); modrm(); mem(size => 16, align => 16); } CVTSI2SS SSE 00001111 00101010 !emit { rep(); modrm(); mem(size => 4); } +CVTSI2SD SSE2 00001111 00101010 !emit { repne(); modrm(); mem(size => 8); } CVTSI2SS_64 SSE 00001111 00101010 !emit { rep(); rex(w => 1); modrm(); mem(size => 8); } +CVTSI2SD_64 SSE2 00001111 00101010 !emit { repne(); rex(w => 1); modrm(); mem(size => 8); } + CVTPS2PI SSE 00001111 00101101 !emit { modrm(); mem(size => 8); } +CVTPD2PI SSE2 00001111 00101101 !emit { data16(); modrm(); mem(size => 16, align => 16); } CVTSS2SI SSE 00001111 00101101 !emit { rep(); modrm(reg => ~REG_ESP); mem(size => 4); } +CVTSD2SI SSE2 00001111 00101101 !emit { repne(); modrm(reg => ~REG_ESP); mem(size => 8); } CVTSS2SI_64 SSE 00001111 00101101 !emit { rep(); rex(w => 1); modrm(reg => ~REG_ESP); mem(size => 4); } +CVTSD2SI_64 SSE2 00001111 00101101 !emit { repne(); rex(w => 1); modrm(reg => ~REG_ESP); mem(size => 8); } + CVTTPS2PI SSE 00001111 00101100 !emit { modrm(); mem(size => 8); } +CVTTPD2PI SSE2 00001111 00101100 !emit { data16(); modrm(); mem(size => 16, align => 16); } CVTTSS2SI SSE 00001111 00101100 !emit { rep(); modrm(reg => ~REG_ESP); mem(size => 4); } +CVTTSD2SI SSE2 00001111 00101100 !emit { repne(); modrm(reg => ~REG_ESP); mem(size => 8); } CVTTSS2SI_64 SSE 00001111 00101100 !emit { rep(); rex(w => 1); modrm(reg => ~REG_ESP); mem(size => 4); } +CVTTSD2SI_64 SSE2 00001111 00101100 !emit { repne(); rex(w => 1); modrm(reg => ~REG_ESP); mem(size => 8); } + +CVTPD2PQ SSE2 00001111 11100110 !emit { repne(); modrm(); mem(size => 16, align => 16); } +CVTTPD2PQ SSE2 00001111 11100110 !emit { data16(); modrm(); mem(size => 16, align => 16); } +CVTDQ2PD SSE2 00001111 11100110 !emit { rep(); modrm(); mem(size => 8); } + +CVTPS2PD SSE2 00001111 01011010 !emit { modrm(); mem(size => 8); } +CVTPD2PS SSE2 00001111 01011010 !emit { data16(); modrm(); mem(size => 16, align => 16); } +CVTSS2SD SSE2 00001111 01011010 !emit { rep(); modrm(); mem(size => 4); } +CVTSD2SS SSE2 00001111 01011010 !emit { repne(); modrm(); mem(size => 8); } + +CVTDQ2PS SSE2 00001111 01011011 !emit { modrm(); mem(size => 16, align => 16); } +CVTPS2DQ SSE2 00001111 01011011 !emit { data16(); modrm(); mem(size => 16, align => 16); } +CVTTPS2DQ SSE2 00001111 01011011 !emit { rep(); modrm(); mem(size => 16, align => 16); } # SSE MXCSR State Management Instructions # LDMXCSR SSE 00001111 10101110 !emit { modrm(mod => ~MOD_DIRECT, reg => 2); mem(size => 4); } @@ -88,6 +162,67 @@ PMULHUW SSE 00001111 11100100 !emit { modrm(); mem(size => 8); } PSADBW SSE 00001111 11110110 !emit { modrm(); mem(size => 8); } PSHUFW SSE 00001111 01110000 !emit { modrm(); mem(size => 8); imm(size => 1); } +# SSE2 128-bit SIMD Integer Instructions +MOVDQA SSE2 00001111 011 d 1111 !emit { data16(); modrm(); mem(size => 16, align => 16); } +MOVDQU SSE2 00001111 011 d 1111 !emit { rep(); modrm(); mem(size => 16); } +MOVQ2DQ SSE2 00001111 11010110 !emit { rep(); modrm(mod => MOD_DIRECT); } +MOVDQ2Q SSE2 00001111 11010110 !emit { repne(); modrm(mod => MOD_DIRECT); } + +PMULUDQ_64 SSE2 00001111 11110100 !emit { modrm(); mem(size => 8); } +PMULUDQ SSE2 00001111 11110100 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PADDB SSE2 00001111 11111100 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PADDW SSE2 00001111 11111101 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PADDD SSE2 00001111 11111110 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PADDQ SSE2 00001111 11010100 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PADDSB SSE2 00001111 11101100 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PADDSW SSE2 00001111 11101101 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PADDUSB SSE2 00001111 11011100 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PADDUSW SSE2 00001111 11011101 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSUBB SSE2 00001111 11111000 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSUBW SSE2 00001111 11111001 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSUBD SSE2 00001111 11111010 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSUBQ_64 SSE2 00001111 11111011 !emit { modrm(); mem(size => 8); } +PSUBQ SSE2 00001111 11111011 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSUBSB SSE2 00001111 11101000 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSUBSW SSE2 00001111 11101001 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSUBUSB SSE2 00001111 11011000 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSUBUSW SSE2 00001111 11011001 !emit { data16(); modrm(); mem(size => 16, align => 16); } + +PSHUFLW SSE2 00001111 01110000 !emit { repne(); modrm(); mem(size => 16, align => 16); imm(size => 1); } +PSHUFHW SSE2 00001111 01110000 !emit { rep(); modrm(); mem(size => 16, align => 16); imm(size => 1); } +PSHUFD SSE2 00001111 01110000 !emit { data16(); modrm(); mem(size => 16, align => 16); imm(size => 1); } + +PSLLW SSE2 00001111 11110001 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSLLW_imm SSE2 00001111 01110001 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 6); imm(size => 1); } +PSLLD SSE2 00001111 11110010 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSLLD_imm SSE2 00001111 01110010 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 6); imm(size => 1); } +PSLLQ SSE2 00001111 11110011 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSLLQ_imm SSE2 00001111 01110011 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 6); imm(size => 1); } +PSLLDQ SSE2 00001111 01110011 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 7); imm(size => 1); } + +PSRAW SSE2 00001111 11100001 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSRAW_imm SSE2 00001111 01110001 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 4); imm(size => 1); } +PSRAD SSE2 00001111 11100010 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSRAD_imm SSE2 00001111 01110010 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 4); imm(size => 1); } + +PSRLW SSE2 00001111 11010001 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSRLW_imm SSE2 00001111 01110001 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 2); imm(size => 1); } +PSRLD SSE2 00001111 11010010 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSRLD_imm SSE2 00001111 01110010 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 2); imm(size => 1); } +PSRLQ SSE2 00001111 11010011 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PSRLQ_imm SSE2 00001111 01110011 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 2); imm(size => 1); } +PSRLDQ SSE2 00001111 01110011 !emit { data16(); modrm(mod => MOD_DIRECT, reg => 3); imm(size => 1); } + +PUNPCKHBW SSE2 00001111 01101000 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PUNPCKHWD SSE2 00001111 01101001 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PUNPCKHDQ SSE2 00001111 01101010 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PUNPCKHQDQ SSE2 00001111 01101101 !emit { data16(); modrm(); mem(size => 16, align => 16); } + +PUNPCKLBW SSE2 00001111 01100000 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PUNPCKLWD SSE2 00001111 01100001 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PUNPCKLDQ SSE2 00001111 01100010 !emit { data16(); modrm(); mem(size => 16, align => 16); } +PUNPCKLQDQ SSE2 00001111 01101100 !emit { data16(); modrm(); mem(size => 16, align => 16); } + # SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions MASKMOVQ SSE 00001111 11110111 !emit { modrm(mod => MOD_DIRECT); mem(size => 8, base => REG_EDI); } MOVNTQ SSE 00001111 11100111 !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); } @@ -97,3 +232,14 @@ PREFETCHT1 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg PREFETCHT2 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 3); mem(size => 1); } PREFETCHNTA SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT, reg => 0); mem(size => 1); } SFENCE SSE 00001111 10101110 !emit { modrm(mod => MOD_DIRECT, reg => 7); } + +# SSE2 Cacheability Control, Prefetch, and Instruction Ordering Instructions +CFLUSH SSE2 00001111 10101110 !emit { modrm(mod => ~MOD_DIRECT, reg => 7); mem(size => 1); } +LFENCE SSE2 00001111 10101110 !emit { modrm(mod => 0b11, reg => 0b101); } +MFENCE SSE2 00001111 10101110 !emit { modrm(mod => 0b11, reg => 0b111); } +PAUSE SSE2 10010000 !emit { rep(); } +MASKMOVDQU SSE2 00001111 11110111 !emit { data16(); modrm(mod => MOD_DIRECT); mem(size => 16, base => REG_EDI); } +MOVNTPD SSE2 00001111 00101011 !emit { data16(); modrm(mod => ~MOD_DIRECT); mem(size => 16, align => 16); } +MOVNTDQ SSE2 00001111 11100111 !emit { data16(); modrm(mod => ~MOD_DIRECT); mem(size => 16, align => 16); } +MOVNTI SSE2 00001111 11000011 !emit { modrm(mod => ~MOD_DIRECT); mem(size => 4); } +MOVNTI_64 SSE2 00001111 11000011 !emit { rex(w => 1); modrm(mod => ~MOD_DIRECT); mem(size => 8); } -- 2.20.1