On Wed, Jun 12, 2019 at 04:41:01PM +0800, Like Xu wrote:
> The CPUID.1F as Intel V2 Extended Topology Enumeration Leaf would be
> exposed if guests want to emulate multiple software-visible die within
> each package. Per Intel's SDM, the 0x1f is a superset of 0xb, thus they
> can be generated by almost same code as 0xb except die_offset setting.
>
> If the number of dies per package is less than 2, the qemu will not
> expose CPUID.1F regardless of whether the host supports CPUID.1F.
>
> Signed-off-by: Like Xu <like...@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabk...@redhat.com>
> ---
> target/i386/cpu.c | 37 +++++++++++++++++++++++++++++++++++++
> target/i386/cpu.h | 4 ++++
> target/i386/kvm.c | 12 ++++++++++++
> 3 files changed, 53 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 09e20a2c3b..127aff74a6 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -4437,6 +4437,42 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
> uint32_t count,
> *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
> }
>
> + assert(!(*eax & ~0x1f));
> + *ebx &= 0xffff; /* The count doesn't need to be reliable. */
> + break;
> + case 0x1F:
> + /* V2 Extended Topology Enumeration Leaf */
> + if (env->nr_dies < 2 || !cpu->enable_cpuid_0x1f) {
> + *eax = *ebx = *ecx = *edx = 0;
> + break;
> + }
> +
> + *ecx = count & 0xff;
> + *edx = cpu->apic_id;
> + switch (count) {
> + case 0:
> + *eax = apicid_core_offset(env->nr_dies, cs->nr_cores,
> + cs->nr_threads);
> + *ebx = cs->nr_threads;
> + *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
> + break;
> + case 1:
> + *eax = apicid_die_offset(env->nr_dies, cs->nr_cores,
> + cs->nr_threads);
> + *ebx = cs->nr_cores * cs->nr_threads;
> + *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
> + break;
> + case 2:
> + *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores,
> + cs->nr_threads);
> + *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
> + *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
> + break;
> + default:
> + *eax = 0;
> + *ebx = 0;
> + *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
> + }
> assert(!(*eax & ~0x1f));
> *ebx &= 0xffff; /* The count doesn't need to be reliable. */
> break;
> @@ -5890,6 +5926,7 @@ static Property x86_cpu_properties[] = {
> DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level,
> true),
> DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
> DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
> + DEFINE_PROP_BOOL("cpuid-0x1f", X86CPU, enable_cpuid_0x1f, true),
> DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
> DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
> DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 69495f0a8a..0434dfb62a 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -726,6 +726,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
> #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
> #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
> +#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
>
> /* MSR Feature Bits */
> #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
> @@ -1444,6 +1445,9 @@ struct X86CPU {
> /* Compatibility bits for old machine types: */
> bool enable_cpuid_0xb;
>
> + /* V2 Compatibility bits for old machine types: */
> + bool enable_cpuid_0x1f;
> +
> /* Enable auto level-increase for all CPUID leaves */
> bool full_cpuid_auto_level;
>
> diff --git a/target/i386/kvm.c b/target/i386/kvm.c
> index 3b29ce5c0d..9b4da9b265 100644
> --- a/target/i386/kvm.c
> +++ b/target/i386/kvm.c
> @@ -1081,6 +1081,10 @@ int kvm_arch_init_vcpu(CPUState *cs)
> }
> break;
> }
> + case 0x1f:
> + if (env->nr_dies < 2 || !cpu->enable_cpuid_0x1f) {
> + break;
> + }
> case 4:
> case 0xb:
> case 0xd:
> @@ -1088,6 +1092,11 @@ int kvm_arch_init_vcpu(CPUState *cs)
> if (i == 0xd && j == 64) {
> break;
> }
> +
> + if (i == 0x1f && j == 64) {
> + break;
> + }
> +
> c->function = i;
> c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
> c->index = j;
> @@ -1099,6 +1108,9 @@ int kvm_arch_init_vcpu(CPUState *cs)
> if (i == 0xb && !(c->ecx & 0xff00)) {
> break;
> }
> + if (i == 0x1f && !(c->ecx & 0xff00)) {
> + break;
> + }
> if (i == 0xd && c->eax == 0) {
> continue;
> }
> --
> 2.21.0
>
--
Eduardo
