On Mon, Jun 24, 2019 at 2:33 AM Palmer Dabbelt <pal...@sifive.com> wrote: > > On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote: > > Based-on: <cover.1555726824.git.alistair.fran...@wdc.com> > > > > Now that the RISC-V spec has started to be ratified let's update our > > QEMU implementation. There are a few things going on here: > > - Add priv version 1.11.0 to QEMU > > - This is the ratified version of the Privledge spec > > - There are almost no changes to 1.10 > > - Mark the 1.09.1 privledge spec as depreated > > - Let's aim to remove it in two releases > > - Set priv version 1.11.0 as the default > > - Remove the user_spec version > > - This doesn't really mean anything so let's remove it > > - Add support for the "Counters" extension > > - Add command line options for Zifencei and Zicsr > > > > We can remove the spec version as it's unused and has never been exposed > > to users. The idea is to match the specs in specifying the version. To > > handle versions in the future we can extend the extension props to > > handle version information. > > > > For example something like this: -cpu rv64,i=2.2,c=2.0,h=0.4,priv_spec=1.11 > > > > NOTE: This isn't supported today as we only have one of each version. > > > > This will be a future change if we decide to support multiple versions > > of extensions. > > > > The "priv_spec" string doesn't really match, but I don't have a better > > way to say "Machine ISA" and "Supervisor ISA" which is what is included > > in "priv_spec". > > > > For completeness I have also added the Counters, Zifencei and Zicsr > > extensions. > > > > Everything else seems to match the spec names/style. > > > > Please let me know if I'm missing something. QEMU 4.1 is the first > > release to support the extensions from the command line, so we can > > easily change it until then. After that it'll take more work to change > > the command line interface. > > > > Alistair Francis (9): > > target/riscv: Restructure deprecatd CPUs > > target/riscv: Add the privledge spec version 1.11.0 > > target/riscv: Comment in the mcountinhibit CSR > > target/riscv: Set privledge spec 1.11.0 as default > > qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 > > target/riscv: Require either I or E base extension > > target/riscv: Remove user version information > > target/riscv: Add support for disabling/enabling Counters > > target/riscv: Add Zifencei and Zicsr as command line options > > > > qemu-deprecated.texi | 8 +++ > > target/riscv/cpu.c | 72 ++++++++++--------- > > target/riscv/cpu.h | 19 ++--- > > target/riscv/cpu_bits.h | 1 + > > target/riscv/csr.c | 13 +++- > > .../riscv/insn_trans/trans_privileged.inc.c | 2 +- > > 6 files changed, 71 insertions(+), 44 deletions(-) > > Aside from the comments on 3 and 9 > > Reviewed-by: Palmer Dabbelt <pal...@sifive.com> > > I've got these, along with my proposed modifications, queued up. LMK if > that's > a problem, particularly the two-patch replacement for 9 needs a review as it's > entirely new code.
I haven't looked at the new code yet, but it all passes my tests so LGTM. Alistair