On Tue, 18 Jun 2019 at 17:55, Cédric Le Goater <c...@kaod.org> wrote: > > When doing calibration, the SPI clock rate in the CE0 Control Register > and the read delay cycles in the Read Timing Compensation Register are > set using bit[11:4] of the DMA Control Register. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> > Acked-by: Joel Stanley <j...@jms.id.au> > --- > hw/ssi/aspeed_smc.c | 64 ++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 63 insertions(+), 1 deletion(-)
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
