The size of the FPU registers depends solely on the floating point
extensions supported by the target architecture.
However, in the previous implementation the floating point register
size was derived from whether the target architecture is 32-bit or
64-bit.
Signed-off-by: Georg Kotheimer <georg.kothei...@kernkonzept.com>
---
configure | 4 ++--
gdb-xml/{riscv-64bit-fpu.xml => riscv-fpu-d.xml} | 0
gdb-xml/{riscv-32bit-fpu.xml => riscv-fpu-f.xml} | 0
target/riscv/gdbstub.c | 15 +++++++--------
4 files changed, 9 insertions(+), 10 deletions(-)
rename gdb-xml/{riscv-64bit-fpu.xml => riscv-fpu-d.xml} (100%)
rename gdb-xml/{riscv-32bit-fpu.xml => riscv-fpu-f.xml} (100%)
diff --git a/configure b/configure
index f2cb9f3c66..462c5a4f1a 100755
--- a/configure
+++ b/configure
@@ -7581,14 +7581,14 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
+ gdb_xml_files="riscv-32bit-cpu.xml riscv-fpu-f.xml riscv-fpu-d.xml
riscv-32bit-csr.xml"
target_compiler=$cross_cc_riscv32
;;
riscv64)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
- gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-fpu-f.xml riscv-fpu-d.xml
riscv-64bit-csr.xml"
target_compiler=$cross_cc_riscv64
;;
sh4|sh4eb)
diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-fpu-d.xml
similarity index 100%
rename from gdb-xml/riscv-64bit-fpu.xml
rename to gdb-xml/riscv-fpu-d.xml
diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-fpu-f.xml
similarity index 100%
rename from gdb-xml/riscv-32bit-fpu.xml
rename to gdb-xml/riscv-fpu-f.xml
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 27be93279b..29fa468b28 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -375,20 +375,19 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
-#if defined(TARGET_RISCV32)
- if (env->misa & RVF) {
+
+ if (env->misa & RVD) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 36, "riscv-32bit-fpu.xml", 0);
+ 36, "riscv-fpu-d.xml", 0);
+ } else if (env->misa & RVF) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 36, "riscv-fpu-f.xml", 0);
}
+#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
4096, "riscv-32bit-csr.xml", 0);
#elif defined(TARGET_RISCV64)
- if (env->misa & RVF) {
- gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
- 36, "riscv-64bit-fpu.xml", 0);
- }
-
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
4096, "riscv-64bit-csr.xml", 0);
#endif
--
2.19.1
