On Wed, 3 Jul 2019 at 09:41, Palmer Dabbelt <pal...@sifive.com> wrote: > > merged tag 'mips-queue-jun-21-2019' > The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: > > Merge remote-tracking branch > 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 > 15:40:50 +0100) > > are available in the Git repository at: > > git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1-v3 > > for you to fetch changes up to 395fd69582a00b76a89c12d9c074055a9d207997: > > hw/riscv: Extend the kernel loading support (2019-06-27 02:47:06 -0700) > > ---------------------------------------------------------------- > RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 > > This pull request contains a handful of patches that I'd like to target > for the 4.1 soft freeze. There are a handful of new features: > > * Support for the 1.11.0, the latest privileged specification. > * Support for reading and writing the PRCI registers. > * Better control over the ISA of the target machine. > * Support for the cpu-topology device tree node. > > Additionally, there are a handful of bug fixes including: > > * Load reservations are now broken by both store conditional and by > scheduling, which fixes issues with parallel applications. > * Various fixes to the PMP implementation. > * Fixes to the 32-bit linux-user syscall ABI. > * Various fixes for instruction decodeing. > * A fix to the PCI device tree "bus-range" property. > > This boots 32-bit and 64-bit OpenEmbedded. > > Changes since v2 [riscv-for-master-4.1-sf1-v2]: > > * Dropped OpenSBI. > > Changes since v1 [riscv-for-master-4.1-sf1]: > > * Contains a fix to the sifive_u OpenSBI integration.
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1 for any user-visible changes. -- PMM