On 7/10/19 7:24 PM, Alex Bennée wrote: > When we converted to using feature bits in 602f6e42cfbf we missed out > the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for > -cpu max configurations. This caused a regression in the GCC test > suite. Fix this by setting the appropriate FP16 bits in mvfr1.FPHP. > > Fixes: https://bugs.launchpad.net/qemu/+bug/1836078 > Signed-off-by: Alex Bennée <alex.ben...@linaro.org> > --- > target/arm/cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index e75a64a25a..0a0a202fe3 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -2452,6 +2452,10 @@ static void arm_max_initfn(Object *obj) > t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); > cpu->isar.id_isar6 = t; > > + t = cpu->isar.mvfr1; > + t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.2 FP16 */
The comment is wrong. This is not full v8.2 FP16 support (which would be value 3, plus a change to SIMDHP), but v8.0 support for double<->half conversions. Otherwise, Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
