Richard Henderson <richard.hender...@linaro.org> writes:
> The VMID is the ASID for the 2nd stage page lookup.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
> ---
> target/arm/helper.c | 26 ++++++++++++++++----------
> 1 file changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 1ed7c06313..3a9f35bf4b 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3452,17 +3452,23 @@ static void vmsa_ttbr_el1_write(CPUARMState *env,
> const ARMCPRegInfo *ri,
> static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> - ARMCPU *cpu = env_archcpu(env);
> - CPUState *cs = CPU(cpu);
> + CPUState *cs = env_cpu(env);
> + int vmid;
>
> - /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
> - if (raw_read(env, ri) != value) {
> - tlb_flush_by_mmuidx(cs,
> - ARMMMUIdxBit_S12NSE1 |
> - ARMMMUIdxBit_S12NSE0 |
> - ARMMMUIdxBit_S2NS);
> - raw_write(env, ri, value);
> - }
> + raw_write(env, ri, value);
> +
> + /*
> + * TODO: with ARMv8.1-VMID16, aarch64 must examine VTCR.VS
> + * (re-evaluating with changes to VTCR) then use bits [63:48].
> + */
> + vmid = extract64(value, 48, 8);
> +
> + /*
> + * A change in VMID to the stage2 page table (S2NS) invalidates
> + * the combined stage 1&2 tlbs (S12NSE1 and S12NSE0).
> + */
> + tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_S2NS,
> + ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0);
> }
>
> static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
--
Alex Bennée
